Semiconductor chips are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the substrate by a thin gate oxide layer, with small portions of the source and drain regions, referred to as "extensions", extending toward and virtually under the gate.
Between the source and drain regions and under the gate oxide layer is a source/drain extension (SDE) region, which is doped. The SDE region typically is doped early in the fabrication process, with the SDE dopant usually being implanted during the steps of forming the gate and source and drain regions. This generally-described structure cooperates to function as a transistor.
To suppress deleterious "short channel" effects such as threshold voltage roll-off (i.e., transistor operation at below intended voltages), it is important that the lateral dopant profile of the source/drain extensions be steep. Stated differently, it is important that virtually all of the dopant be concentrated within a relatively small area that is to function as the source/drain extension, with little or no dopant being located outside this relatively small doped region.
The present invention recognizes that the dopant gradient is deleteriously affected by high thermal budgets and particularly by high temperatures, such as those typically required during annealing to activate the dopant. Stated differently, exposing dopant in a source/drain extension to high temperatures can cause the dopant to thermally diffuse and, hence, can cause the dopant profile undesirably to spread. Nonetheless, the dopant must be activated for the device to function properly. The present invention has considered the above problem and has provided the solutions disclosed herein.